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? semiconductor components industries, llc, 2016 august, 2016 ? rev. 2 1 publication order number: ncv8878/d ncv8878 automotive grade start-stop non-synchronous boost controller the ncv8878 is a non-synchronous boost controller designed to supply a minimum output voltage during start-stop vehicle operation battery voltage sags. the controller drives an external n-channel mosfet. the device uses peak current mode control with internal slope compensation. the ic incorporates an internal regulator that supplies charge to the gate driver. protection features include, cycle-by-cycle current limiting and thermal shutdown. additional features include low quiescent current sleep mode operation. the ncv8878 is enabled when the supply voltage drops below the wake up threshold. boost operation is initiated when the supply voltage drops below the regulation set point. features ? automatic enable below wake up threshold voltage (factory programmable) ? status pin diagnostic function ? override disable function ? boost mode operation at regulation set point ? 2% output accuracy over temperature range ? peak current mode control with internal slope compensation ? wide input voltage range of 2 v to 40 v, 45 v load dump ? low quiescent current in sleep mode (<12 a typical) ? cycle ? by ? cycle current limit protection ? hiccup ? mode overcurrent protection (ocp) ? thermal shutdown (tsd) ? this is a pb ? free device typical applications ? applications requiring regulated voltage through cranking and start ? stop operation marking diagram www. onsemi.com soic ? 8 d suffix case 751 1 8 pin connections 1 8 2 3 4 7 6 5 (top view) status isns gnd gdrv disb vc vout vdrv 8878xx = specific device code xx = 01 or 11 a = assembly location l = wafer lot y = year w = work week = pb ? free package 8878xx alyw 1 8 device package shipping ? ordering information NCV887801D1R2G soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncv8878 www. onsemi.com 2 figure 1. typical application battery in status cc rc cdrv nvmfs5844nl nrvb440fs lp vdrv gnd isns status vout disb gdrv vc rsns co cg vout figure 2. functional waveforms v micro mbr2045fmfs disable wake up threshold wakeup disb status battery in vout regulation sleep threshold gdrv wake up delay comp gdrv switching delay internal clamp voltage package pin descriptions pin no. pin symbol function 1 status this is an open ? drain diagnostic. ic status operation flag indicator. this output is a logic low when ic vout is below the wake up threshold voltage (th ic,en ) and device is active. a pull ? up resistor of around 80 k should be connected between status and a microcontroller reference. this output is a logic high when the ic is disabled or in uvlo. 2 isns current sense input. connect this pin to the source of the external n ? mosfet, through a current ? sense res- istor to ground to sense the switching current for regulation and current limiting. 3 gnd ground reference. 4 gdrv gate driver output. connect to gate of the external n ? mosfet. a series resistance can be added from gdrv to the gate to tailor emc performance. 5 vdrv driving voltage. internally ? regulated supply for driving the external n ? mosfet, sourced from vout. bypass with a 1.0 f ceramic capacitor to ground. 6 vout monitors output voltage and provides ic input voltage. 7 vc output of the voltage error transconductance amplifier. an external compensator network from vc to gnd is used to stabilize the converter. 8 disb disable input. this part is disabled when this pin is brought low.
ncv8878 www. onsemi.com 3 absolute maximum ratings (voltages are with respect to gnd, unless otherwise indicated) rating value unit dc supply voltage (vout) ? 0.3 to 40 v peak transient voltage (load dump on vout) 45 v dc supply voltage (vdrv, gdrv) 12 v dc voltage (vc, isns) ? 0.3 to 3.6 v dc voltage (disb, status) ? 0.3 to 6 v dc voltage stress (vout ? vdrv) ? 0.7 to 40 v operating junction temperature ? 40 to 150 c storage temperature range ? 65 to 150 c peak reflow soldering temperature: pb ? free, 60 to 150 seconds at 217 c 265 peak c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. package capabilities characteristic value unit esd capability (all pins) human body model 2.0 kv moisture sensitivity level 1 package thermal resistance junction ? to ? ambient, r ja (note 1) 100 c/w 1. 1 in 2 , 1 oz copper area used for heatsinking. typical values part no. d max f s s a v cl i src i sink vout sce ncv887801 83% 450 khz 53 mv/ s 200 mv 800 ma 600 ma 6.8 v n
ncv8878 www. onsemi.com 4 electrical characteristics ( ? 40 c < t j < 150 c, 3.6 v < v out < 40 v, unless otherwise specified) min/max values are guaranteed by test, design or statistical correlation. characteristic symbol conditions min typ max unit general quiescent current, sleep mode i q,sleep v out = 13.2 v, t j = 25 c, disb = 0 v ? 12 14 a quiescent current, no switching i q,off into v out pin, vout,reg < v out < vout,des, no switching ? 2.2 4.0 ma oscillator switching frequency f sw ncv887801 405 450 495 khz minimum pulse width t on,min 90 115 145 ns maximum duty cycle d max 81 83 85 % slope compensating ramp (note 2) s a ncv887801 46 53 60 mv/ s status flag status wake up delay v out < 7.3 v th ic,en ? 9.3 14 s status pull ? down capability sinking 1.0 ma ? ? 400 mv disable disb pull ? down current (note 2) i dis v dis = 5 v ? 0.6 1.0 a disb input high voltage v d,ih 2.0 ? 5.0 v disb input high voltage hysteresis v d,hys ? 500 ? mv disb input low voltage v d,il 0 ? 800 mv current sense amplifier low ? frequency gain a csa input ? to ? output gain at dc, isns 1 v 0.9 1.0 1.1 v/v bandwidth bw csa gain of a csa ? 3 db 2.5 ? ? mhz isns input bias current i sns,bias out of isns pin ? 30 50 a current limit threshold voltage v cl voltage on isns pin ncv887801 180 200 220 mv current limit, response time (note 2) t cl cl tripped until gdrv falling edge, v isns = v cl (typ) + 60 mv ? 80 125 ns overcurrent protection, threshold voltage %v ocp percent of v cl 125 150 175 % overcurrent protection, response time (note 2) t ocp from overcurrent event, until switching stops, v isns = v ocp + 40 mv ? 80 125 ns voltage error operational transconductance amplifier transconductance g m,vea v out = 100 mv 0.8 1.2 1.63 ms vea output resistance (note 2) r o,vea 2.0 ? ? m ? vea maximum output voltage v c,max 2.5 ? ? v vea sourcing current i src,vea vea output current, vc = 2.0 v 80 100 ? a vea sinking current i snk,vea vea output current, vc = 1.5 v 80 100 ? a vea clamp voltage v c,clamp v out < vout,des ? 1.1 ? v gdrv switching delay v out < vout,des or when ic disb goes from low to high with vc pin compensation network disconnected ? 55 64 s gate driver sourcing current i src v drv typical driving voltage specifica- tion, v drv ? v gdrv = 2 v 550 800 ? ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design.
ncv8878 www. onsemi.com 5 electrical characteristics ( ? 40 c < t j < 150 c, 3.6 v < v out < 40 v, unless otherwise specified) min/max values are guaranteed by test, design or statistical correlation. characteristic unit max typ min conditions symbol gate driver sinking current i sink v gdrv 2 v 480 600 ? ma driving voltage dropout (note 2) v drv,do v out ? v drv , iv drv = 25 ma ? 0.3 0.6 v driving voltage source current i drv v out ? v drv = 1 v 35 45 ? ma backdrive diode voltage drop v d,bd v drv ? v out , i d,bd = 5 ma ? ? 0.7 v driving voltage v drv i vdrv = 0.1 ? 25 ma 5.8 6.0 6.2 v pull ? down resistance ? 21 ? k uvlo undervoltage lock ? out, threshold voltage v uvlo,fall v out falling 3.40 3.59 3.80 v undervoltage lock ? out v uvlo, rise v out rising 3.90 4.05 4.20 v thermal shutdown thermal shutdown threshold (note 2) t sd t j rising 160 170 180 c thermal shutdown hysteresis (note 2) t sd,hys t j falling 10 15 20 c thermal shutdown delay (note 2) t sd,dly from t j > t sd to stop switching ? ? 100 ns voltage regulation voltage regulation vout ,reg ncv887801 6.66 6.80 6.94 v threshold ic enable v out descending ncv887801 7.10 7.30 7.50 v threshold ic disable v out ascending ncv887801 7.55 7.75 7.95 v threshold ic enable ? voltage reg- ulation ncv887801 0.32 0.5 ? v threshold ic disable ? threshold ic enable ncv887801 ? 0.4 ? v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design.
ncv8878 www. onsemi.com 6 typical characteristics 15 i q,sleep , sleep current ( a) t j , junction temperature ( c) figure 3. sleep current vs. temperature 510 30 15 20 i q,sleep , sleep current ( a) v out , output voltage (v) figure 4. sleep current vs. v out 14 13 12 11 10 30 25 20 15 10 5 124 t on,min , minimum on time (ns) t j , junction temperature ( c) figure 5. quiescent current vs. temperature ? 50 0 150 50 100 123 122 121 120 119 118 117 116 115 1.020 normalized current limit t j , junction temperature ( c) figure 6. minimum on time vs. temperature ? 50 0 150 50 100 1.005 1.000 0.990 0.980 normalized v out regulation (v) t j , junction temperature ( c) figure 7. normalized current vs. temperature ? 50 0 150 50 100 1.000 0.998 0.996 figure 8. v out regulation vs. temperature ? 50 0 150 50 100 v out = 13.2 v 0.995 0.985 1.010 1.015 1.002 1.004 1.006 150 c ? 50 0 150 50 100 i q,off , quiescent current (ma) t j , junction temperature ( c) 2.20 2.18 2.16 2.14 2.12 25 25 c ? 40 c disb = 0 v v out = v out,reg < v out descending f s = 450 khz
ncv8878 www. onsemi.com 7 typical characteristics 4.1 uvlo threshold (v) t j , junction temperature ( c) figure 9. switching frequency vs. temperature ? 50 0 15 0 50 100 4.0 3.9 3.8 3.7 3.6 vout rising vout falling 7.2 threshold ic voltage (v) t j , junction temperature ( c) figure 10. uvlo threshold vs. temperature ? 50 0 150 50 100 7.8 7.7 7.6 7.5 7.4 7.3 enable disable 750 i disb , pulldown current (na) t j , junction temperature ( c) figure 11. ncv887801 threshold ic voltage vs. temperature ? 50 0 150 50 100 700 650 600 550 500 figure 12. disb pulldown current vs. temperature switching frequency (khz) t j , junction temperature ( c) ? 50 0 150 50 100 450 449 448 447 446 445 444
ncv8878 www. onsemi.com 8 theory of operation figure 13. current mode control schematic oscillator slope compensation + q q set clr s r ncv8878 voltage error vea csa pwm comparator gate drive compensation l isns gdrv vout wakeup disb disable gnd vc (optional) status status nrvb440fs nvmfs5844nl r l c o v output v in r sns r damp c decoupling v micro disb the disb pin provides an ic disable function. when a dc logic-low voltage is applied to this pin, the ncv8878 enters a low quiescent sleep mode, permitting an external signal to either shutdown the ic or disable the wakeup function. regulation the ncv8878 is a non ? synchronous boost controller designed to supply a minimum output voltage during start ? stop vehicle operation battery voltage sags. the ncv8878 is in low quiescent current sleep mode under normal battery operation (12 v) and is enabled when the supply voltage drops below the descending threshold (7.3 v for the ncv887801). boost operation is initiated when the supply voltage is below the regulation set point (6.8 v for the ncv887801). once the supply voltage sag condition ends and begins to increase, the ncv8878 boost operation will cease when the supply voltage increases beyond the regulation set point. the ncv8878 low quiescent current sleep mode resumes once the supply voltage increases beyond the ascending voltage threshold (7.7 v for the ncv887801). the ncv8878 vout pin serves the dual purpose: (1) powering the ncv8878 and (2) providing the regulation feedback signal. the feedback network is imbedded within the ic to eliminate the constant current battery drain that would exist with the use of external voltage feedback resistors. there is no soft ? start operating mode. the ncv8878 will instantly respond to a voltage sag so as to maintain normal operation of downstream loads. once the ncv8878 is enabled, the voltage error operational transconductance amplifier supplies current to set vc to 1.1 v to minimize the feedback loop response time when the battery voltage sag goes below the regulation set point. current mode control the ncv8878 incorporates a current mode control scheme, in which the pwm ramp signal is derived from the power switch current. this ramp signal is compared to the output of the error amplifier to control the on ? time of the power switch. the oscillator is used as a fixed ? frequency clock to ensure a constant operational frequency. the resulting control scheme features several advantages over conventional voltage mode control. first, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. this eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. the second benefit comes from inherent pulse ? by ? pulse current limiting by merely clamping the peak switching current. finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. this allows for a simpler compensation. the ncv8878 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. a proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. current limit the ncv8878 features two current limit protections, peak current mode and over current latch off. when the current sense amplifier detects a voltage above the peak current limit between isns and gnd after the current limit
ncv8878 www. onsemi.com 9 leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. set the current limit with a resistor from isns to gnd, with r = v cl / i limit . if the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. the device will remain off for the hiccup time and then go through the soft ? start procedure. uvlo input undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when vin is too low to support the internal rails and power the controller. the ic will start up when enabled and vin surpasses the uvlo threshold plus the uvlo hysteresis and will shut down when vin drops below the uvlo threshold or the part is disabled. vdrv an internal regulator provides the drive voltage for the gate driver. bypass with a ceramic capacitor to ground to ensure fast turn on times. the capacitor should be between 0.1 f and 1 f, depending on switching speed and charge requirements of the external mosfet. vdrv uses an internal linear regulator to charge the vdrv bypass capacitor . vout must be decoupled at the ic by a capacitor that is equal or larger in value than the vdrv decoupling capacitor. application information design methodology this section details an overview of the component selection process for the ncv8878 in continuous conduction mode boost. it is intended to assist with the design process but does not remove all engineering design work. many of the equations make heavy use of the small ripple approximation. this process entails the following steps: 1. define operational parameters 2. select current sense resistor 3. select output inductor 4. select output capacitors 5. select input capacitors 6. select compensator components 7. select mosfet(s) 8. select diode 9. design notes 10. determine feedback loop compensation network 1. define operational parameters before beginning the design, define the operating parameters of the application. these include: v in(min) : minimum input voltage [v] v in(max): maximum input voltage [v] v out : output voltage [v] i out(max) : maximum output current [a] i cl : desired typical cycle-by-cycle current limit [a] from this the ideal minimum and maximum duty cycles can be calculated as follows: d min 1 v in(max) v out d max 1 v in(min) v out both duty cycles will actually be higher due to power loss in the conversion. the exact duty cycles will depend on conduction and switching losses. if the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. this is because a boost converter cannot have an output lower than the input. in situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. if the calculated d max is higher the d max of the ncv8878, the conversion will not be possible. it is important for a boost converter to have a restricted d max , because while the ideal conversion ration of a boost converter goes up to infinity as d approaches 1, a real converter?s conversion ratio starts to decrease as losses overtake the increased power transfer. if the converter is in this range it will not be able to regulate properly. if the following equation is not satisfied, the device will skip pulses at high v in : d min f s t on(min) where: f s : switching frequency [hz] t on(min) : minimum on time [s] 2. select current sense resistor current sensing for peak current mode control and current limit relies on the mosfet current signal, which is measured with a ground referenced amplifier. the easiest method of generating this signal is to use a current sense resistor from the source of the mosfet to device ground. the sense resistor should be selected as follows: r s v cl i cl where: r s : sense resistor [ ] v cl : current limit threshold voltage [v] i cl : desire current limit [a] 3. select output inductor the output inductor controls the current ripple that occurs over a switching period. a high current ripple will result in excessive power loss and ripple current requirements. a low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. a good starting point for peak to peak ripple is around 20 ? 40% of the inductor current at the maximum load at the worst case v in , but operation should be verified empirically. the worst case v in is half of v out , or whatever v in is closest to half of v out . after choosing a peak current ripple value, calculate the inductor value as follows:
ncv8878 www. onsemi.com 10 l v in(wc) d wc i l,max f s where: v in(wc) : v in value as close as possible to half of v out [v] d wc : duty cycle at v in(wc) i l,max : maximum peak to peak ripple [a] the maximum average inductor current can be calculated as follows: i l,avg v out i out(max) v in(min) the peak inductor current can be calculated as follows: i l,peak i l,avg i l,max 2 where: i l,peak : peak inductor current value [a] 4. select output capacitors the output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. the steady state output ripple associated with the output capacitors can be calculated as follows: v out(ripple) di out(max) f c out i out(max) 1 d v in(min) d 2 f l r esr the capacitors need to survive an rms ripple current as follows: i cout(rms) i out d wc d wc d wc 12 d wc l r out
t sw 2 the use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. 5. select input capacitors the input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. i cin(rms) v in(wc) 2 d wc l f s v out 23 6. select compensator components current mode control method employed by the ncv8878 allows the use of a simple, t ype ii compensation to optimize the dynamic response according to system requirements. 7. select mosfet(s) in order to ensure the gate drive voltage does not drop out the mosfet(s) chosen must not violate the following inequality: q g(total) i drv f s where: q g(total) : total gate charge of mosfet(s) [c] i drv : drive voltage current [a] f s : switching frequency [hz] the maximum rms current can be calculated as follows: i q(max) i out d d the maximum voltage across the mosfet will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: v q(max) v out(max) 8. select diode the output diode rectifies the output current. the average current through diode will be equal to the output current: i d(avg) i out(max) additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: v d(max) v out(max) the maximum power dissipation in the diode can be calculated as follows: p d v f (max) i out(max) where: p d : power dissipation in the diode [w] v f(max) : maximum forward voltage of the diode [v]
ncv8878 www. onsemi.com 11 9. design notes ? vout serves a dual purpose (feedback and ic power). the vdrv circuit has a current pulse power draw resulting in current flow from the output sense location to the ic. trace esl will cause voltage ripple to develop at ic pin vout which could affect performance. ? use a 1 f ic vout pin decoupling capacitor close to ic in addition to the vdrv decoupling capacitor. ? classic feedback loop measurements are not possible (vout pin serves a dual purpose as a feedback path and ic power). feedback loop computer modeling recommended. ? a step load test for stability verification is recommended. ? compensation ground must be dedicated and connected directly to ic ground. ? do not use vias. use a dedicated ground trace. ? ic ground & current sense resistor ground sense point must be located on the same side of pcb. ? vias introduce sufficient esr/esl voltage drop which can degrade the accuracy of the current feedback signal amplitude (signal bounce) and should be avoided. ? star ground should be located at ic ground pad. ? this is the location for connecting the compensation and current sense grounds. ? the ic architecture has a leading edge isns blanking circuit. in some instances, current pulse leading edge current spike rc filter may be required. ? if required, 330 pf + 250 are a recommended evaluation starting point. ? r damping (optional) ? the ic-vout pin may be located a few cm from the output voltage sensing point. parasitic inductance from the feedback trace (roughly 5 nh/cm) results in the requirement for a decoupling capacitor (c decoupling = 1 f recommended) next to the ic-vout pin to support the vdrv charging pulses. the ic-vdrv energy is replenished from current pulses by an internal linear regulator whose charging frequency corresponds to that of the ic oscillator (phase lag may occur; some charging pulses may occasionally be skipped depending on the state of the vdrv voltage). the trace?s parasitic inductance can introduce a low amplitude damped voltage oscillation between the ic-vout and the output voltage sense location which may result in minor frequency jitter. ? if the measured frequency jitter is objectionable, it may be attenuated by placing a series damping resistor (r damp ) in the feedback path between the output voltage sense and ic-vout. the resulting filter introduced by r damp introduces a high frequency pole in the feedback loop path. the rc filter 3 db pole frequency must be chosen at a minimum of 1 decade above the design?s feedback loop cross-over frequency (at minimum power supply input voltage where the worst case phase margin will occur) to avoid deteriorating the feedback loop cross-over frequency phase margin . ? the average operating current demand from the ic is dominated by the mosfet gate drive power energy consumption (i vdrv = q g (tot)_6v x f osc ). the i vdrv x r damp voltage drop results in a corresponding increase in power supply regulation voltage. r damp is typically 0.68 , so the resulting increase in output voltage regulation will be minimal (10-30 mv may be typical) . 10. determine feedback loop compensation network the purpose of a compensation network is to stabilize the dynamic response of the converter. by optimizing the compensation network, stable regulation response is achieved for input line and load transients. compensator design involves the placement of poles and zeros in the closed loop transfer function. losses from the boost inductor, mosfet, current sensing and boost diode losses also influence the gain and compensation expressions. the ota has an esd protection structure ( r esd 502 , data not provided in the datasheet) located on the die between the ota output and the ic package compensation pin (vc). the information from the ota pwm feedback control signal (v ctrl ) may differ from the ic ? vc signal if r 2 is of similar order of magnitude as r esd . the compensation and gain expressions which follow take influence from the ota output impedance elements into account . type ? i compensation is not possible due to the presence of r esd . the figure 14 compensation network corresponds to a type ? ii network in series with r esd . the resulting control ? output transfer function is an accurate mathematical model of the ic in a boost converter topology. the model does have limitations and a more accurate spice model should be considered for a more detailed analysis: ? the attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor esr is not considered in the equations . ? the efficiency term should be a reasonable operating condition estimate.
ncv8878 www. onsemi.com 12 rds(on) v d l r i c out v out c 1 r 2 v in r l r cf c 2 r out gnd isns vout gdrv vc v ctrl ota r esd r 1 r low r 0 v ref figure 14. ncv8878 ota and compensation a worksheet as well as a spice model which may be used for selecting compensation components r 2 , c 1 , c 2 is available at the on semiconductor web site (http://onsemi.com/powersolutions/product.do?id=ncv8 878 ). the following equations may be used to analyze the figure 1 0 boost converter. required input design parameters for analysis are: v d = boost diode v f (v) v in = boost supply input voltage (v) r i = current sense resistor ( ) r ds(on) = mosfet r ds(on) ( ) c out = bulk output capacitor value (f) r sw_eq = r ds(on) + r i , for the boost continuous conduction mode (ccm) expressions r cf = bulk output capacitor esr ( ) r out = equivalent resistance of output load ( ) p out = output power (w) l = boost inductor value (h) r l = boost inductor esr ( ) t s = 1/f s , where f s = clock frequency (hz) v out = device specific output voltage (e.g. 6.8 v for ncv887801) (v) v ref = ota internal voltage reference = 1.2 v r 0 = ota output resistance = 3 m s a = ic slope compensation (e.g. 53 mv/ s for ncv887801) g m = ota transconductance = 1.2 ms d = controller duty ratio d? = 1 ? d
ncv8878 www. onsemi.com 13 necessary equations for describing the modulator gain (v ctrl ? to ? v out gain) h ctrl_output(f) are described in table 1. table 1. boost ccm transfer function expressions duty ratio (d) 2r out v d v in r sw_eq r out v in v out 2 v out 2 ? v out r out r out v in 2 2r sw_eq v in v out 4v d r sw_eq v in ? 4r sw_eq v out 2 4r l v d v in 4r l v out 2 r sw_eq 2 v out 2 2r out v out 2 v d v in v out /v in power supply dc con- version ratio (m) 1 1 d average inductor current (i lave ) p out v in inductor on ? slope (s n ) v in i lave r l r sw_eq l r i compensation ramp (m c ) 1 s a s n c out esr zero ( z1 ) 1 r cf c out right ? half ? plane zero ( z2 ) ( 1 d ) 2 l r out r cf r out r cf r out r l l low frequency modulator pole ( p1 ) 2 r out t s lm 3 m c c out sampling double pole ( n ) t s sampling quality coefficient (q p ) 1 ( m c ( 1 d ) 0.5 ) f m 1 2m r out t s lm 2 1 2 s a s n h d r out r i control ? output transfer function (h ctrl_output (f)) f m h d 1 j 2 f z1 1 j 2 f p1 j 2 f z2 1 j 2 f n q p j 2 f n 2 once the desired cross ? over frequency (f c ) gain adjustment and necessary phase boost are determined from the h ctrl_output (f) gain and phase plots, the table 2 equations may be used. it should be noted that minor compensation component value adjustments may become necessary when r 2 ~10 r esd as a result of approximations for determining components r 2 , c 1 , c 2 .
ncv8878 www. onsemi.com 14 table 2. ota compensation transfer function and compensation values desired ota gain at cross ? over frequency f c (g) 10 desired_g fc_gain_db 20 desired phase boost at cross ? over frequency f c (boost) margin arg h ctrl_output ( fc ) 180 90 180 select ota compensation zero to coincide with modulator pole at f p1 (f z ) p1e 2 resulting ota high frequency pole placement (f p ) f z f c f c 2 tan(boost) f c f z tan(boost) compensation resistor (r 2 ) f p g f p f z v out 1.2 g m 1 f c f p 2 1 f z f p compensation capacitor (c 1 ) 1 2 f z r 2 compensation capacitor (c 2 ) 1 2 f p g 1.2 g m v out ota dc gain (g 0_ota ) v ref v out g m r 0 low frequency zero ( z1e ) 1 2 r 2 r esd r 2 r esd c 2 1 1 4 r 2 r esd c 2 r 2 r esd 2 c 1 high frequency zero ( z2e ) 1 2 r 2 r esd r 2 r esd c 2 1 1 4 r 2 r esd c 2 r 2 r esd 2 c 1 low frequency pole ( p1e ) 1 2 r 0 r 2 r esd r 2 r 0 r esd c 2 1 1 4 r 2 r 0 r esd c 2 r 0 r 2 r esd 2 c 1 high frequency pole ( p2e ) 1 2 r 0 r 2 r esd r 2 r 0 r esd c 2 1 1 4 r 2 r 0 r esd c 2 r 0 r 2 r esd 2 c 1 ota transfer function (g ota (f)) ? g 0_ota 1 j 2 f z1e 1 j 2 f p1e 1 j 2 f z2e 1 j 2 f p2e the open ? loop ? response in closed ? loop form to verify the gain/phase margins may be obtained from the following expressions. t(f) g ota (f)h ctrl_output (f)
ncv8878 www. onsemi.com 15 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncv8878/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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